Cooling schedules for optimal annealing
Mathematics of Operations Research
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Models for iterative global optimization
Models for iterative global optimization
Circuit Placement, Chip Optimization, and Wire Routing for IBMIC Technology
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Potential-NRG: placement with incomplete data
DAC '98 Proceedings of the 35th annual Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
METRICS: a system architecture for design process optimization
Proceedings of the 37th Annual Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Meta-Heuristics: Theory and Applications
Meta-Heuristics: Theory and Applications
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Design technology productivity in the DSM era (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Routing-aware scan chain ordering
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routing-aware scan chain ordering
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Incremental component implementation selection: enabling ECO in compositional system synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The incremental, "construct by correction" design methodology has become widespread in constraint-dominated DSM design. We study the problem of ECO for physical design domains in the general context of incremental optimization. We observe that an incremental design methodology is typically built from a full optimizer that generates a solution for an initial instance, and an incremental optimizer that generates a sequence of solutions corresponding to a sequence of perturbed instances. Our hypothesis is that in practice, there can be a mismatch between the strength of the incremental optimizer and the magnitude of the perturbation between successive instances. When such a mismatch occurs, the solution quality will degrade -- perhaps to the point where the incremental optimizer should be replaced by the full optimizer. We document this phenomenon for three distinct domains -- partitioning, placement and routing -- using leading industry and academic tools. Our experiments show that current CAD tools may not be correctly designed for ECO-dominated design processes. Thus, compatibility between optimizer and instance perturbation merits attention both as a research question and as a matter of industry design practice.