Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Post-routing timing optimization with routing characterization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Optimal partitioners and end-case placers for standard-cell layout
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Interconnect estimation and planning for deep submicron designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Retiming for DSM with area-delay trade-offs and delay constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
Multiple Si layer ICs: motivation, performance analysis, and design implications
Proceedings of the 37th Annual Design Automation Conference
Synthesis for multiple input wires replacement of a gate for wiring consideration
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Delay-optimal wiring plan for the microprocessor of high performance computing machines
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 international workshop on System-level interconnect prediction
Faster and more accurate wiring evaluation in interconnect-centric floorplanning
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Analysis and optimization of thermal issues in high-performance VLSI
Proceedings of the 2001 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Proceedings of the 39th annual Design Automation Conference
Constraint-driven communication synthesis
Proceedings of the 39th annual Design Automation Conference
The future of logic synthesis and verification
Logic Synthesis and Verification
Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits
Analog Integrated Circuits and Signal Processing
On mismatches between incremental optimizers and instance perturbations in physical design tools
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Challenges in physical chip design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coupled analysis of electromigration reliability and performance in ULSI signal nets
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Exploring regular fabrics to optimize the performance-cost trade-off
Proceedings of the 40th annual Design Automation Conference
Design of Asynchronous Controllers with Delay Insensitive Interface
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Boosting: Min-Cut Placement with Improved Signal Delay
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Statistically Aware Buffer Planning
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement
Journal of VLSI Signal Processing Systems
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Time Budgeting in a Wireplanning Context
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Novel Metric for Interconnect Architecture Performance
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Thermal Modeling, Characterization and Management of On-Chip Networks
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Exploiting level sensitive latches in wire pipelining
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Temperature-Aware On-Chip Networks
IEEE Micro
Processing Rate Optimization by Sequential System Floorplanning
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-chip bus thermal analysis and optimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
On the decreasing significance of large standard cells in technology mapping
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Wire retiming as fixpoint computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speed indicators for circuit optimization
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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A shift is proposed in the design of VLSI circuits. In conventional design, higher levels of synthesis produce a netlist, from which layout synthesis builds a mask specification for manufacturing. Timing analysis is built into a feedback loop to detect timing violations which are then used to update specifications to synthesis. Such iteration is undesirable, and for very high performance designs, infeasible. The problem is likely to become much worse with future generations of technology. To achieve a non-iterative design flow, we propose that early synthesis stages should use “wireplanning” to distribute delays over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays. In this paper we attempt to quantify this problem for future technologies and propose some solutions for a “constant delay” methodology.