Design of Asynchronous Controllers with Delay Insensitive Interface

Authors:
Hiroshi Saito;Takashi Nanya;Alex Kondratyev
Affiliations:
The university of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8904, Japan;The university of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo, 153-8904, Japan;Cadence Design Systems, 2001 Addison St., 3rd floor, Berkeley, CA
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

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Abstract

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents a new approach for synthesis of globally DI and locally SI circuits suggested in [7]. The method starts from a speed-independent implementation and locally modifies gate functions to ensure their independence from delays in communication wires. The suggested approach was successfully tested on a set of benchmarks.