Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
DAC '98 Proceedings of the 35th annual Design Automation Conference
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
CAD directions for high performance asynchronous circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
A high-performance asynchronous SCSI controller
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Towards Asynchronous A-D Conversion
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Design of Asynchronous Controllers with Delay Insensitive Interface
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
STG Optimisation in the Direct Mapping of Asynchronous Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
The magic rule of tiles: virtual delay insensitivity
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous speed-independent (SI) circuits, whose behaviour is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioural specification, for which Signal Transition Graph, an interpreted Petri net, is used. The method is successfully tested on a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40% for area and 20% for speed.