Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Communication and Concurrency
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Design and Analysis of a Self-Timed Duplex Communication System
IEEE Transactions on Computers
| Hi-index | 0.00 |
Direct mapping from Petri nets (PN) and Signal Transition Graphs (STG) avoids algorithmic complexity inherent in logic synthesis methods based on optimal state encoding. However, it may lead to inefficient implementation, both in size and performance, due to excessive use of state-holding elements.This paper presents a set of tools that optimise logic produced by the direct mapping technique by means of: exposure of outputs, detection and elimination of redundant places. Output exposure is an approach to explicitly model output signals as STG places, which can be directly mapped into output flip-flops. The STG can be simplified after output exposure. The detection of redundant places is a computationally hard problem with multiple solutions. The tool solves this problem by using several heuristics aimed at speed and size. All operations preserve behavioural equivalence. The efficiency of the overall algorithm and individual heuristics is analysed using a number of benchmarks.