Integration, the VLSI Journal
Automatic synthesis of burst-mode asynchronous controllers
Automatic synthesis of burst-mode asynchronous controllers
Symbolic Model Checking
Asynchronous System on Chip Interconnect
Asynchronous System on Chip Interconnect
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Asynchronous Control Device Design by Net Model Behavior Simulation
Proceedings of the 17th International Conference on Application and Theory of Petri Nets
Designing an asynchronous pipeline token ring interface
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
STG Optimisation in the Direct Mapping of Asynchronous Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Petri net translation patterns for the analysis of ebusiness collaboration messaging protocols
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
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Communication-centric design is a key paradigm for systems-on-chips (SoCs), where most computing blocks are predesigned IP cores. Due to the problems with distributing a clock across a large die, future system designs will be more asynchronous or self-timed. For portable, battery-run applications, power and pin efficiency is an important property of a communication system where the cost of a signal transition on a global interconnect is much greater than for internal wires in logic blocks. The paper addresses this issue by designing an asynchronous communication system aimed at power and pin efficiency. Another important issue of SoC design is design productivity. It demands new methods and tools, particularly for designing communication protocols and interconnects. The design of a self-timed communication system is approached employing formal techniques supported by verification and synthesis tools. The protocol is formally specified and verified with respect to deadlock-freedom and delay-insensitivity using a Petri-net-based model-checking tool. A protocol controller has been synthesized by a direct mapping of the Petri net model derived from the protocol specification. The logic implementation was analyzed using the Cadence toolkit. The results of SPICE simulation show the advantages of the direct mapping method compared to logic synthesis.