Implementation and analysis of the TRIMOSBUS self-clocking interface
Automatic Control and Computer Sciences
Towards fault-tolerant hardware implementation of physical layer network protocols
Automatic Control and Computer Sciences
Automatic Control and Computer Sciences
The Post Office experience: designing a large asynchronous chip
Integration, the VLSI Journal - Special issue on asynchronous systems
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
Wire-OR Logic on Transmission Lines
IEEE Micro
Is the Die Cast for the Token Game?
ICATPN '02 Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Design and Analysis of a Self-Timed Duplex Communication System
IEEE Transactions on Computers
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
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We describe the design of a speed-independent interface based on a pipeline token-ring architecture. The original goal was to build a reliable communication medium, able to tolerate up to two faults in any segment of the ring, to be used in an on-board multicomputer. We believe that the pipeline ring approach can help reduce some negative "analogue" effects inherent in asynchronous buses (including on-chip ones) by means of using only "point-to-point" interconnections. We briefly outline the major ideas of the channel's organisation, protocol and our syntax-driven implementation of the channel protocol controller. The protocol has been recently verified for deadlock-freedom and fairness.