Communications of the ACM
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
The design of a high-performance cache controller: a case study in asynchronous synthesis
Integration, the VLSI Journal - Special issue on asynchronous systems
The Post Office experience: designing a large asynchronous chip
Integration, the VLSI Journal - Special issue on asynchronous systems
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
A high-performance asynchronous SCSI controller
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
High-Level Design of an Asynchronous Packet-Routing Chip
Proceedings of the Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits
A CMOS VLSI Implementation of an Asynchronous ALU
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Automated Synthesis of Asynchronous Interface Circuits
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Designing an asynchronous pipeline token ring interface
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Synthesis of Asynchronous Controllers for Heterogeneous Systems
Synthesis of Asynchronous Controllers for Heterogeneous Systems
An asynchronous matrix-vector multiplier for discrete cosine transform
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A New Control Circuit for Asynchronous Micropipelines
IEEE Transactions on Computers
A Macroscopic Behavior Model for Self-Timed Pipeline Systems
Proceedings of the seventeenth workshop on Parallel and distributed simulation
A clocking technique for FPGA pipelined designs
Journal of Systems Architecture: the EUROMICRO Journal
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early set to zero micro-pipeline
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
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This paper presents design and simulation results of two high-performance asynchronous pipeline circuits. The first circuit is a two-phase micropipeline but uses pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for data storage in place of traditional transmission gate latches or Sutherland's capture-pass latches. The second circuit is a four-phase micropipeline with burst-mode control circuits. We compare our DETDFF and four-phase implementations of a FIFO buffer with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor. We implemented Day and Woods's design and both of our designs in the MOSIS 1.2 /spl mu/m CMOS process and simulated them with a 4.6 V power supply and at 100/spl deg/C. Our SPICE simulations show that our DETDFF and four-phase designs have 70% and 30% higher throughput respectively than Day and Woods's design. This higher throughput for the DETDFF design is due to latching the data on both edges of the latch control, removing the need of a reset phase and simplifying the control structures. Our four-phase design, on the other hand, has higher throughput because of the simplified control structures and the removal of the latch enable buffers from the critical path. The four-phase design, though not quite as fast as the DETDFF design, requires much smaller area for data storage.