Communications of the ACM
SHILPA: a high-level synthesis system for self-timed circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Checking Delay-Insensitivity: 104 Gates and Beyond
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Improving self-timed pipeline ring performance through the addition of buffer loops
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
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This paper presents a novel macroscopic behavior modelfor self-timed pipeline (STP). STP is a promising architecturefor system-on-chip (SoC) design, because STP easesthe timing problems and abnegates the control dependenciesamong building components to prevent the parallelismand integrity. In earlier evaluation processes, a cycle-basedsimulation takes too long and too much memory to surveythe wandering behavior of STP. From the theoretical pointof view, throughput of a STP system depends on the occupiedrate. This leads to the production of our new model,which only manages the position and velocity of packets.Our behavior model omits the precise status of each stage ina pipeline to save these simulation costs. Simulators basedon the existing naive model and on our model show equivalentresults, while the latter is about 1.5 to 5 times fasterthan the former. Both models are applied to a ring style STPwhich is used in real processor's hardware implementation.Also, a 4 multiprocessor system connected by STP networkexecuting an image processing was successfully simulated.