High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Fourteen Ways to Fool Your Synchronizer
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
A Practical Introduction to Computer Architecture
A Practical Introduction to Computer Architecture
Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems
Micro-pipeline section for condition-controlled loop
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Non-linear asynchronous micro-pipelines
Proceedings of the 12th International Conference on Computer Systems and Technologies
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A micro-pipeline, which consists of one-cycle and multi-cycle micro-pipeline units, is considered. Along with the purpose to design unified and independent of the micro-pipeline unit structure control circuit, a unified interpretation of the pipeline organization is proposed. This interpretation sets to foreground the write to pipeline register micro-operation. The implementation of a pipeline according to that interpretation is limited by the type of the registers, used to store the pipeline stage data, which are registers using only one edge (rising or falling). The mentioned limitation necessitates the usage of four-phase pipeline unit communication protocols. Accordingly, an asynchronous micro-pipeline and its control are designed. The control is capable of combining the two types of micro-pipeline units. The operation of the protocol is shown.