Communications of the ACM
High-Speed Non-Linear Asynchronous Pipelines
Proceedings of the conference on Design, automation and test in Europe
Detection and Generation of Self-Timed Pipelines from High Level Specifications
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
Conditional Acknowledge Synchronisation in Asynchronous Interconnect Switch Design
AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
Micro-pipeline section for condition-controlled loop
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
Early set to zero micro-pipeline
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
Race condition free asynchronous micro-pipeline units
Proceedings of the 11th International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing on International Conference on Computer Systems and Technologies
A Designer's Guide to Asynchronous VLSI
A Designer's Guide to Asynchronous VLSI
| Hi-index | 0.00 |
The paper considers structural problems in synthesis of micro-pipelines which implement algorithms with conditional jumps. These structures require pre-definition of the term "micro-pipeline". As a result there are defined, analyzed and described four new scientific tasks necessary for solving this common problem. The paper presents the solution of only one of the tasks -- synthesis of micro-pipeline that controls section generating value of the transition condition, as well as the connection of this section with initial stage controllers into both branches. The complete logical synthesis is explained and as a result logical structures of pipeline controllers are obtained in two variants: for 2-phase data transfer protocol and for 4-phase data transfer protocol.