Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
A modular synchronizing FIFO for NoCs
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
N-way ring and square arbiters
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A low latency wormhole router for asynchronous on-chip networks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
Reconfigurable controllers for synchronization via wagging
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Microelectronics Journal
Non-linear asynchronous micro-pipelines
Proceedings of the 12th International Conference on Computer Systems and Technologies
Truncation error analysis of MTBF computation for multi-latch synchronizers
Microelectronics Journal
The magic rule of tiles: virtual delay insensitivity
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
International Journal of Embedded and Real-Time Communication Systems
Metastability challenges for 65nm and beyond: simulation and measurements
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
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Todays networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance synchronizers and arbiters. Written by one of the foremost researchers in this area of digital design, this authoritative text provides in-depth theory and practical design solutions for the reliable working of synchronization and arbitration hardware in digital systems. The book provides methods for making real reliability measurements both on and off chip, evaluating some of the common difficulties and detailing circuit solutions at both circuit and system levels. Synchronization and Arbitration in Digital Systems also presents: mathematical models used to estimate mean time between failures in digital systems; a summary of serial and parallel communication techniques for on-chip data transmission; explanations on how to design a wrapper for a locally synchronous cell, highlighting the issues associated with stoppable clocks; an examination of various types of priority arbiters, using signal transition graphs to show the specification of different designs (from the simplest to more complex multi-way arbiters) including ways of solving problems encountered in a wide range of applications; essential information on systems composed of independently timed regions, including a discussion on the problem of choice and the factors affecting the time taken to make choices in electronics. With its logical approach to design methodology, this will prove an invaluable guide for electronic and computer engineers and researchers working on the design of digital electronic hardware. Postgraduates and senior undergraduate students studying digital systems design as part of their electronic engineering course will struggle to find a resource that better details the information given inside this book