Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
Metastable Behavior in Digital Systems
IEEE Design & Test
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
The Devolution of Synchronizers
ASYNC '10 Proceedings of the 2010 IEEE Symposium on Asynchronous Circuits and Systems
Metastability and Synchronizers: A Tutorial
IEEE Design & Test
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Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and below. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system is shown that accounts for changes in delay values due to supply voltage and temperature changes. We present a detailed comparison of measurements and simulations for a fabricated 65nm bulk CMOS circuit and discuss implications of the measurements for synchronization systems in 65nm and beyond. We propose an adaptive self-calibrating synchronizer to account for supply voltage, temperature, global process variations and DVFS.