Degradation Delay Model Extension to CMOS Gates
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
A Metastability-Free Multi-synchronous Communication Scheme for SoCs
SSS '09 Proceedings of the 11th International Symposium on Stabilization, Safety, and Security of Distributed Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Formal verification of synchronizers
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Metastability challenges for 65nm and beyond: simulation and measurements
Proceedings of the Conference on Design, Automation and Test in Europe
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Fault-free digital circuits may malfunction when asynchronous inputs have critical timing combinations that result in metastableoperation. This mode of failure is often overlooked in digital system design and reliability analysis. Here, we survey developmentsin the study of metastable behavior and identify their relevance to digital system design and reliability, and we describeand evaluate a number of techniques for reducing the probability of metastable failure.