The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
What is the cost of delay insensitivity?
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Modular Approach to Multi-resource Arbiter Design
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
Asynchronous spatial division multiplexing router
Microprocessors & Microsystems
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Delay-insensitivity is a theoretically attractive design principle which helps circuits to be resistant to process variations, particularly exhibiting them selves at the system level as delay variations. Unfortunately, delay insensitive (DI) design is impractical for most real systems. Speed independent (SI) design is often used in practice as a next best approach. With the scaling of wires becom ing more and more difficult compared with logic gates at current and future technology nodes, SI systems are becoming less acceptable as “approximates” for DI systems. This paper proposes an approach based on decomposing complex systems into simple, manageable blocks which can be safely rendered in an SI manner. These blocks are then connected using interconnects which satisfy DI requirements to obtain “virtual DI” behaviour at system level. We demonstrate this approach with a tile-based implementation of a multi-access arbiter.