On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Journal of VLSI Signal Processing Systems
Delay-Insensitivity and Semi-Modularity
Formal Methods in System Design
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Self-Timed Carry-Lookahead Adders
IEEE Transactions on Computers - Special issue on computer arithmetic
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes
IEEE Transactions on Computers
Self-timed cellular automata and their computational ability
Future Generation Computer Systems - Cellular automata CA 2000 and ACRI 2000
True Concurrency in Models of Asynchronous Circuit Behavior
Formal Methods in System Design
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
General Conditions for the Decomposition of State-Holding Elements
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Dynamic Hazards and Speed Independent Delay Model
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Some Limitations to Speed-Independence in Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Self-Timed Implementation of Boolean Functions
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous DRAM Design and Synthesis
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Monotonic Circuits with Complete Acknowledgement
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Delay-Insensitive Carry-Lookahead Adders
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Concurrent computing machines and physical space-time
Mathematical Structures in Computer Science
Highly pipelined asynchronous FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An ultra low-power processor for sensor networks
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Testing delay faults in asynchronous handshake circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Hazard-free self-timed design: methodology and application
Integrated Computer-Aided Engineering
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust asynchronous implementation of Boolean functions on the basis of duality
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
Concurrent rewriting semantics and analysis of asynchronous digital circuits
WRLA'10 Proceedings of the 8th international conference on Rewriting logic and its applications
Self-timed SRAM for energy harvesting systems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
A syntax-directed translation for the synthesis of delay-insensitive circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving the robustness of self-timed SRAM to variable Vdds
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
QDI decomposed DIMS method featuring homogeneous/heterogeneous data encoding
ICANCM'11/ICDCC'11 Proceedings of the 2011 international conference on applied, numerical and computational mathematics, and Proceedings of the 2011 international conference on Computers, digital communications and computing
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
The magic rule of tiles: virtual delay insensitivity
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
Reversible delay-insensitive distributed memory modules
RC'13 Proceedings of the 5th international conference on Reversible Computation
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