The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Design of Asynchronous Circuits Assuming Unbounded Gate Delays
IEEE Transactions on Computers
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
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In this paper, we discuss Three-Rail coded 2-phase signaling self-timed implementation of Boolean functions by feedback-free gate networks. Delays in operating Three-Rail gates and signals associated with inputs and outputs of gates are assumed to be arbitrary but finite. We implement some Three-Rail gates by binary Boolean gates. In implemented Three-Rail gates we assume isochronic forks or equipotential regions. We show that Three-Rail gates are the smallest gates, such that the feedback-free gate networks are self-timed under 2-phase protocol. Designing Three-Rail feedback- free gate networks is as hard as designing corresponding synchronous feedback-free gate networks.