The Design and Use of Hazard-Free Switching Networks
Journal of the ACM (JACM)
A State Variable Assignment Method for Asynchronous Sequential Switching Circuits
Journal of the ACM (JACM)
Ideas of asynchronous feedback networks
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
Design criteria for autosynchronous circuits
AIEE-ACM-IRE '58 (Eastern) Papers and discussions presented at the December 3-5, 1958, eastern joint computer conference: Modern computers: objectives, designs, applications
Reliable High-Speed Arbitration and Synchronization
IEEE Transactions on Computers
Dynamic Hazards and Speed Independent Delay Model
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Self-Timed Implementation of Boolean Functions
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Systems of Asynchronously Operating Modules
IEEE Transactions on Computers
Towards a Theory of Universal Speed-Independent Modules
IEEE Transactions on Computers
Autotesting Speed-Independent Sequential Circuits
IEEE Transactions on Computers
Asynchronous Sequential Machines Designed for Fault Detection
IEEE Transactions on Computers
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region
IEEE Transactions on Computers
On the Design of Three-Valued Asynchronous Modules
IEEE Transactions on Computers
The Effect of Asynchronous Inputs on Sequential Network Reliability
IEEE Transactions on Computers
Direct Implementation of Asynchronous Control Units
IEEE Transactions on Computers
On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
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This paper considers the general problem of the synthesis of asynchronous combinational and sequential circuits based on the assumption that gate delays may be unbounded and that line delays are suitably constrained. Certain problems inherent to circuit realizations with unbounded gate delays are discussed and methods of solving them are proposed. Specific synthesis techniques are presented for both combinational and sequential circuits. The use of completion detection necessitated by the assumption of unbounded gate delays also causes the circuits to stop operating for approximately half of all possible single faults, thus achieving a degree of self-checking.