Petri nets and speed independent design
Communications of the ACM
Logic Design: A Review of Theory and Practice
Logic Design: A Review of Theory and Practice
Introduction to Switching Theory and Logical Design
Introduction to Switching Theory and Logical Design
Modular Asynchronous Control Design
IEEE Transactions on Computers
Self-Synchronizing Circuits and Nonfundamental Mode Operation
IEEE Transactions on Computers
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes
IEEE Transactions on Computers
Design of Asynchronous Circuits Assuming Unbounded Gate Delays
IEEE Transactions on Computers
A multiprocessor system design
AFIPS '63 (Fall) Proceedings of the November 12-14, 1963, fall joint computer conference
A functional description of macromodules
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Is the Die Cast for the Token Game?
ICATPN '02 Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets
Counterflow Pipeline Based Dynamic Instruction Scheduling
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A technique for making asynchronous sequential circuits readily testable
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Design and test of self-checking asynchronous control circuit
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Output feedback control of asynchronous sequential machines with disturbance inputs
Information Sciences: an International Journal
| Hi-index | 14.98 |
The "one-hot" row assignment for asynchronous circuits, in which every row in a flow table has exactly one of the feedback variables that equals the value 1, provides a straightforward method for circuit synthesis. Once a flow table has been constructed, the state equations can be directly written, without requiring any procedure to ensure a race-free assignment. Furthermore, it can implement any arbitrary fundamental mode asynchronous circuit, not depending on a specific signaling protocol for its correct operation. An alternate view of one-hot asynchronous circuits is given, with a simple set-reset flip-flop for each state. Although this may seem excessive compared to implementations with encoded state variables, for many circuits their one-hot implementation is comparable in cost to other asynchronous implementations.