Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
Direct Implementation of Asynchronous Control Units
IEEE Transactions on Computers
Fault detection experiments for asynchronous sequential machines
SWAT '70 Proceedings of the 11th Annual Symposium on Switching and Automata Theory (swat 1970)
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A design technique for making asynchronous (unclocked) sequential circuits easily testable is given. Through the addition of (1) one or at most two state variables; (2) one input lead; and (3) the use of one or more observable output leads, we achieve scan-out and also make the given machine strongly connected. Verification of proper operation can then proceed as in classical machine identification previously restricted to synchronous designs. An example of the implementation of our technique is given for the case where the 1-out-of-n state assignment is used.