An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors
IEEE Transactions on Computers
Q-Modules: Internally Clocked Delay-Insensitive Modules
IEEE Transactions on Computers
Communications of the ACM
Multiple, out-of-order, instruction issuing system for superscalar processors
Multiple, out-of-order, instruction issuing system for superscalar processors
An out-of-order superscalar processor with speculative execution and fast, precise interrupts
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Direct Implementation of Asynchronous Control Units
IEEE Transactions on Computers
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This paper proposes a new dynamic instruction scheduler called the Asynchronous Fast Dispatch Stack (AFDS). This approach utilizes asynchronous design techniques to implement a dispatch stack-based dynamic instruction issue mechanism. To maintain throughput and simplify dependency computations, the AFDS architecture includes a counterflow pipeline, which is modeled after the Counterflow Pipeline Processor (CFPP) proposed by Sproull and Sutherland. The AFDS counterflow pipeline, however, propagates instruction dependency and completion information, rather than results and source operands. Preliminary results indicate that the AFDS is a promising application of the CFPP architecture.