Additional comments on a problem in concurrent programming control
Communications of the ACM
Solution of a problem in concurrent programming control
Communications of the ACM
COORDINATION OF ASYNCHRONOUS EVENTS
COORDINATION OF ASYNCHRONOUS EVENTS
IEEE Transactions on Computers
Transition Logic Circuits and a Synthesis Method
IEEE Transactions on Computers
Anomalous Behavior of Synchronizer and Arbiter Circuits
IEEE Transactions on Computers
A Theory of Asynchronous Control Networks
IEEE Transactions on Computers
Asynchronous Sequential Switching Circuits with Unrestricted Input Changes
IEEE Transactions on Computers
Design of Asynchronous Circuits Assuming Unbounded Gate Delays
IEEE Transactions on Computers
Events and conditions: introduction
Record of the Project MAC conference on concurrent systems and parallel computation
Modular, asynchronous control structures for a high performance processor
Record of the Project MAC conference on concurrent systems and parallel computation
On maximally parallel schemata
SWAT '70 Proceedings of the 11th Annual Symposium on Switching and Automata Theory (swat 1970)
SWCT '64 Proceedings of the 1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Logical design of macromodules
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Systematic design for modular realization of control functions
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
The general synthesis problem for asynchronous digital networks
FOCS '67 Proceedings of the 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)
Journal of Computer and System Sciences
Monotonic Circuits with Complete Acknowledgement
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Delay-insensitive computation in asynchronous cellular automata
Journal of Computer and System Sciences
Construction universality in purely asynchronous cellular automata
Journal of Computer and System Sciences
Self-Synchronizing Circuits and Nonfundamental Mode Operation
IEEE Transactions on Computers
On the Design of Three-Valued Asynchronous Modules
IEEE Transactions on Computers
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Modeling Communication with Synchronized Environments
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Fluctuation-driven computing on number-conserving cellular automata
Information Sciences: an International Journal
Implementation of handshake components
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
Modeling Communication with Synchronized Environments
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Embedding Universal Delay-Insensitive Circuits in Asynchronous Cellular Spaces
Fundamenta Informaticae - Cellular Automata
Reversible delay-insensitive distributed memory modules
RC'13 Proceedings of the 5th international conference on Reversible Computation
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Of concern here are asynchronous modules, i.e., those whose activity is regulated by initiation and completion signals with no clocks being present. First a number of operating conditions are described that are deemed essential or useful in a system of asynchronous modules, while retaining an air of independence of particular hardware implementations as much as possible. Second, some results are presented concerning sets of modules that are universal with respect to these conditions. That is, from these sets any arbitrarily complex module may be constructed as a network. It is stipulated that such constructions be speed independent, i.e., independent of the delay time involved in any constituent modules. Furthermore it is required that the constructions be delay insensitive in the sense that an arbitrary number of delay elements may be inserted into or removed from connecting lines without effecting the external behavior of the network.