Towards a Theory of Universal Speed-Independent Modules
IEEE Transactions on Computers
A Scheme for Synchronizing High-Speed Logic: Part I
IEEE Transactions on Computers
| Hi-index | 0.01 |
The inherent problems of data transmission in a strictly feedforward line have been discussed in the literature. In such a line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, if time variations exist in the delays of successive stages then there is always a nonzero probability that two successive control pulses will eventually appear at the inputs to a given stage so closely spaced that the basic reaction time necessary for the stage to accommodate to new conditions will be violated. If each stage of the line is associated with an independent information symbol, then the inevitable result of such an interaction is the failure of the basic transfer mechanism and a consequent loss of information, i.e., an error. This weakness of the feedforward transfer mechanism is not due to individual stage failures, for it is assumed that all pertinent stage characteristics are bounded, but rather to the compiled effects of an arbitrary number of cascaded stages. Hence tighter design bounds on the individual stages can only lessen--not eliminate--the problem. Rather, the cause of this basic weakness is related to the fact that the control impulse that indexes information forward in the feedforward register line is Moving in the same direction as the flow of information. Inevitably, the loss of a control pulse midway along a line results in part of the string of symbols on the line (that part of the string that has been traversed by the impulse) moving forward relative to the symbol string ahead of it (not traversed by the impulse), hence in an overlap in the information stored on the line. Although actual information loss could be postponed in such a cascade pf stages by utilizing redundancy--e.g., by the utilization of a multivalued symbol alphabet capable of compacting the information as necessary--only a finite and predetermined amount of such compacting could be provided by physically realizable stages. Attacking this basic weakness of the feedforward scheme seems to result in a solution that avoids the problem altogether. If the control pulse moved in a direction opposite to the direction of information flow, that is if the control and information flows are antiparallel, then the loss of a control pulse would leave a void, or hole, in the information stored on the line. Indeed, an arbitrarily large number of such losses could only result in a greater and greater dispersion of a given amount of information (rather than a greater degree of overlapping), but would imply no necessary loss of information, nor a physically unrealizable storage requirement on the individual stages. In this paper this suggested alternative case is examined, and an antiparallel register stage is proposed. In lines composed of such stages the control pulses that index information forward on the line flow in the direction opposite to that of the information flow. The characteristics of such stages are described, as well as the augmentations that permit its adaptation to the construction of general logic networks and systems. Realizations of an antiparallel stage are presented in terms of conventional logical elements, as well as extensions of the stage to include logical fan-in and fan-out. Problems of network structure are considered, including cascaded trees and loops. Finally, a basic modification of the antiparallel stage is discussed that is capable of autonomous stimulation, and that also aids in the elimination of voids which occur during processing.