The limitations to delay-insensitivity in asynchronous circuits
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The paper studies a class of asynchronous circuits in which every signal transition on the inputs of every gate is acknowledged during the circuit operation. This property is called complete acknowledgement (CA) and it is considered here for circuits that consist of gates described by monotonic boolean functions only.In order to implement such circuits the standard CMOS designs of 2-input logic gates are modified by using an additional output for CA. The paper investigates the behavioral properties of monotonic CA (MCA) circuits and the feasibility of a behavioral specification to be refined to a CA-implementable form. The resultof comparison of a number of CA realizations with their speed-independent counterparts produced by negative gate synthesis inspires optimism about the practicality of CA circuits. Being particularly robust to variations in technological parameters, e.g. the value and type of delay and switching thresholds, such circuits offer potential advantages for future CMOS designs.