Towards a Theory of Universal Speed-Independent Modules
IEEE Transactions on Computers
IEEE Transactions on Computers
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region
IEEE Transactions on Computers
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
IEEE Transactions on Computers
IEEE Transactions on Computers
The Effect of Asynchronous Inputs on Sequential Network Reliability
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Asynchronous speed-independent arbiter in a form of a hardware control module
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
N-way ring and square arbiters
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
General theory of metastable operation
IEEE Transactions on Computers
A low latency asynchronous arbitration circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.01 |
When two or more processors attempt to simultaneously use a functional unit (memory, multiplier, etc.), an arbiter module must be employed to insure that processor requests are honored in sequence. The design of asynchronous arbiters is complicated because multiple input changes are allowed, and because inputs may change even if the circuit is not in a stable state. A practical arbiter and its implementation are presented. Implementation of various priority rules (linear, ring, mixed) is discussed, and building large arbiters with trees of two-user arbiters is considered.