Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
The switching structure and addressing architecture of an extensible multiprocessor: cm*.
The switching structure and addressing architecture of an extensible multiprocessor: cm*.
IEEE Transactions on Computers
A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
IEEE Transactions on Computers
Interference Analysis of Shuffle/Exchange Networks
IEEE Transactions on Computers
Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Sequential stopping rules for the regenerative method of simulation
IBM Journal of Research and Development
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Performance Models of Asynchronous Multitrunk HYPERchannel Networks
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
IWCC '01 Proceedings of the NATO Advanced Research Workshop on Advanced Environments, Tools, and Applications for Cluster Computing-Revised Papers
A Parallel System Architecture Based on Dynamically Configurable Shared Memory Clusters
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Reduction of Connections for Multibus Organization
IEEE Transactions on Computers
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Performance analysis of future shared storage systems
IBM Journal of Research and Development
A combinatorial approach to performance analysis of a shared-memory multiprocessor
COCOON'99 Proceedings of the 5th annual international conference on Computing and combinatorics
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
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In this paper we compare the effective bandwidth in a multiprocessor with shared memory using as interconnection networks the crossbar or the multiple-bus. We consider a system with N processors and N memory modules, in which the processor requests to the memory modules are independent and uniformly distributed random variables. We consider two cases: in the first the processor makes another request immediately after a memory service, and in the second there is some internal processing time.