Bandwidth availability of multiple-bus multiprocessors
IEEE Transactions on Computers
Performance of multiple-bus interconnections for multiprocessors
Journal of Parallel and Distributed Computing
The Stanford Dash Multiprocessor
Computer
Programming environment for phase-reconfigurable parallel programming on SuperNode
Journal of Parallel and Distributed Computing
Effective cache prefetching on bus-based multiprocessors
ACM Transactions on Computer Systems (TOCS)
Synchronization and communication in the T3E multiprocessor
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Data Forwarding in Scalable Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Advanced Computer Architectures
Advanced Computer Architectures
Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approach
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
Cache Injection: A Novel Technique for Tolerating Memory Latency in Bus-Based SMPs
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
A survey of distributed shared memory systems
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
An Architecture based on the Memory Mapped Node Addressing in Reconfigurable Interconnection Network
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Embedded Cluster Computing through Dynamic Reconfigurability of Inter-Processor Connections
IWCC '01 Proceedings of the NATO Advanced Research Workshop on Advanced Environments, Tools, and Applications for Cluster Computing-Revised Papers
Task Scheduling for Dynamically Configurable Multiple SMP Clusters Based on Extended DSC Approach
PPAM '01 Proceedings of the th International Conference on Parallel Processing and Applied Mathematics-Revised Papers
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
Dynamic SMP clusters with communication on the fly
ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
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The paper presents a new architectural solution for parallel systems built of shared memory processor clusters. The system is based on dynamically run-time reconfigurable multi-processor clusters; each organized around a local shared memory module placed in a common address space. Each memory module is accessed by a local cluster bus and a common inter-cluster bus. Programs are organized accordingly to their macro dataflow graphs in which tasks and communication are so defined, as to eliminate reloading of data caches during task execution. The behaviour of the proposed system has been evaluated by simulation based on an extended macro dataflow graph representation that includes modelling of data bus arbiters in the system. Program distribution into dynamic processor clusters assumes run-time switching of processors between busses and memory modules. It can reduce contention on data busses. CG algorithm execution in the proposed architecture shows seed-up greater than 4 when 5 busses are applied instead of one.