A semi-markov model for the performance of multiple-bus systems
IEEE Transactions on Computers
Performance of unbuffered shuffle-exchange networks
IEEE Transactions on Computers - The MIT Press scientific computation series
Analysis of multiple-bus interconnection networks
Journal of Parallel and Distributed Computing
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Approximate Methods for Analyzing Queueing Network Models of Computing Systems
ACM Computing Surveys (CSUR)
Concrete Math
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
Interference in Multiprocessor Systems with Localized Memory Access Probabilities
IEEE Transactions on Computers
An Analysis of Processor-Memory Interconnection Networks
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Effects of storage contention on system performance
IBM Systems Journal
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A unified approach is proposed for performance analysis of an N × M shared-memory multiprocessor system, consisting of N processors and M memory modules, each of which may be 'hot' and/or 'favorite'. Processors are allowed to have non-uniform memory access patterns and unsatisfied requests are queued up in the buffers of the corresponding modules. The system performance is measured in terms of the effective bandwidth, which is the average number of busy memory modules in one cycle. Our analytical approach, based on the combinatorial arguments as well as queuing models, estimates the bandwidth with good accuracy for arbitrary values of N and M. These estimations tally very well with the simulation results. Since the presence of a hot module almost always leads to an accumulation of memory requests in its direction and thus deteriorates the system performance, one may expect that the hotness should be spread over as many (say, K) modules as possible. However, simulation results showed an upper bound on K beyond which the bandwidth either drops or saturates. From the approximate queuing model, we derive those saturation values in terms of N, M and ph (the probability of accessing a hot module by a processor).