Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Multiprocessors with Private Cache Memories
IEEE Transactions on Computers
Binary Search in a Multiprocessing Environment
IEEE Transactions on Computers
Reduction of Connections for Multibus Organization
IEEE Transactions on Computers
Interference Analysis of Shuffle/Exchange Networks
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Performance analysis of future shared storage systems
IBM Journal of Research and Development
| Hi-index | 15.02 |
An approximate analysis is performed of an often studied model of an interleaved memory, multiprocessor system consisting of M memory modules and N processors. A closed-form solution is obtained and the one approximation used is found to result in negligible error. This solution is about an order of magnitude more accurate than the best previous result.