Architecture of a New Microprocessor
Computer
Microsystems Microprocessor Networks
Computer
On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System
IEEE Transactions on Computers
Models for Dynamic Load Balancing in a Heterogeneous Multiple Processor System
IEEE Transactions on Computers
Direct A Multiprocessor Organization for Supporting Relational Database Management Systems
IEEE Transactions on Computers
Interleaved Memory Bandwidth in a Model of a Multiprocessor Computer System
IEEE Transactions on Computers
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Hi-index | 14.98 |
Continuing technological advances in single-chip intelligence and storage cell density, and in bulk store performance provide increasing opportunities to construct multiple microprocessor systems. The objective of this experimental study was to explore the performance of selected system architectures in a manner sufficiently detailed, quantitative and realistic to 1) contribute to our understanding of the fundamental behavior of such systems and 2) permit practical designs to follow from the results.