Modeling Bus Contention and Memory Interference in a Multiprocessor System
IEEE Transactions on Computers
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Multiple-Read Single-Write Memory and Its Applications
IEEE Transactions on Computers
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
A Comparative Study of Distributed Resource Sharing on Multiprocessors
IEEE Transactions on Computers
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
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This paper studies one of the most difficult and important problems in the design of cost-effective multiple-microprocessor systems. The combined effect of interference due to bus contentions and that due to memory conflicts is investigated. Reference models are defined and applied to obtain analytic results which can prove to be valuable tools in the design of multiple-microprocessor systems for time-critical control processes. The effect of memory mapping is also investigated and an algorithm is developed to obtain a mapping which can be used to minimize memory conflicts.