Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
Theory, Volume 1, Queueing Systems
Theory, Volume 1, Queueing Systems
On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System
IEEE Transactions on Computers
Interference in Multiprocessor Systems with Localized Memory Access Probabilities
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
Multiple-Read Single-Write Memory and Its Applications
IEEE Transactions on Computers
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
A systematic approach to the design of digital bussing structures
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Cm*: a modular, multi-microprocessor
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Modeling Bus Contention and Memory Interference in a Multiprocessor System
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Application note: Internal communications in a multiprocessor ISDN PBX
Computer Communications
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
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Markovian models are developed for the performance analysis and comparison of several single bus multiprocessor architectures. Processors are assumed to cooperate in a message passing fashion, and messages are exchanged through common memory areas. Four architectures are considered in this paper which differ in the location of the common memory modules. Contention for shared resources is modeled and the corresponding efficiency loss is studied. Numerical results are obtained for the processing power of each architecture, introducing simplifying assumptions that allow a compact Markovian system description.