Analytic models for memory interference in multiprocessor computer systems.
Analytic models for memory interference in multiprocessor computer systems.
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
AFIPS '72 (Spring) Proceedings of the May 16-18, 1972, spring joint computer conference
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
Effects of storage contention on system performance
IBM Systems Journal
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Vector Computer Memory Bank Contention
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Reduction of memory interference in multiprocessor systems
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
IEEE Transactions on Computers
Modeling Bus Contention and Memory Interference in a Multiprocessor System
IEEE Transactions on Computers
Approximate Models of Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Markov Models for Multiple Bus Multiprocessor Systems
IEEE Transactions on Computers
Performance of Cross-Bar Multiprocessor Systems
IEEE Transactions on Computers
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
IEEE Transactions on Computers
Architecture Optimization of Aerospace Computing Systems
IEEE Transactions on Computers
Memory Interference in Synchronous Multiprocessor Systems
IEEE Transactions on Computers
A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Memory Interference Models with Variable Connection Time
IEEE Transactions on Computers
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
IEEE Transactions on Computers
Analytic modeling of network processors for parallel workload mapping
ACM Transactions on Embedded Computing Systems (TECS)
Performance analysis of future shared storage systems
IBM Journal of Research and Development
A conflict-free traffic assignment algorithm using forward planning
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 3
Performance analysis of common bus multimicroprocessor systems
Journal of Systems and Software
On the product-form solution of a class of multiple-bus multiprocessor system models
Journal of Systems and Software
| Hi-index | 15.03 |
This paper presents a mathematical model for determining the extent of memory interference in multiprocessor systems. The model takes into account the numbers of processors and memory modules in the system and their relative service times, as well as the patterns of memory accesses made by the processors. The results predicted by the model are compared with simulation results and with results from other exact or approximate models, where these exist.