Interference in multiprocessor computer systems with interleaved memory
Communications of the ACM
An analysis of the instruction execution rate in certain computer structures
An analysis of the instruction execution rate in certain computer structures
A General Model for Memory Interference in Multiprocessors
IEEE Transactions on Computers
Using cache memory to reduce processor-memory traffic
25 years of the international symposia on Computer architecture (selected papers)
A process cache memory for tightly coupled multiprocessor systems
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Interconnection unit for Poly-Processor System: Analysis and design
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
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This paper reports results of a study to determine and compare the effectiveness of various techniques aimed at reducing memory interference in multiprocessor multi memory systems. A simulation model of a multiprocessor, driven by address traces, is used for evaluation purposes. Two approaches to interference reduction are considered, being the reduction of overlapping memory requirements through various memory allocation methods, and the use of local memory to reduce the request rate to shared memory. Both private and cache memory are considered for this purpose.