4.2BSD and 4.3BSD as examples of the UNIX system
ACM Computing Surveys (CSUR) - The MIT Press scientific computation series
Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
A class of compatible cache consistency protocols and their support by the IEEE futurebus
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Cache memory optimization to reduce processor/memory traffic
Advances in VLSI and Computer Systems
CLIPPER 32-bit microprocessor: user's manual
CLIPPER 32-bit microprocessor: user's manual
Event-driven debugging for distributed software
Microprocessors & Microsystems
The Balance Multiprocessor System
IEEE Micro
Firefly: A Multiprocessor Workstation
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
IEEE Transactions on Computers
Implementing a cache consistency protocol
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Multiprocessor Organization—a Survey
ACM Computing Surveys (CSUR)
Experience Using Multiprocessor Systems—A Status Report
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Communications of the ACM
Advances in Computer Architecture
Advances in Computer Architecture
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Using cache memory to reduce processor-memory traffic
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
An economical solution to the cache coherence problem
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Reduction of memory interference in multiprocessor systems
ISCA '77 Proceedings of the 4th annual symposium on Computer architecture
IEEE Transactions on Parallel and Distributed Systems
A process cache memory for tightly coupled multiprocessor systems
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture
Revised Papers from the NETWORKING 2002 Workshops on Web Engineering and Peer-to-Peer Computing
Fine-grain design space exploration for a cartographic SoC multiprocessor
ACM SIGARCH Computer Architecture News
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The implementation of a coherence protocol and the cache-memory architecture for a Clipper-based multiprocessor prototype is described. The Clipper was chosen for its high-performance features: fast clock speed, internal caches, internal dual buses, sophisticated pipelining system, and integrated execution units. Previous experience in which a common bus caused the main performance bottleneck motivated the use of a private cache for each processor. The coherence protocol, called reduced state transitions (RST), is a modification of the Dragon protocol. In particular, the high performance of RST results from sophisticated architectural solutions, such as the use of buffers and overlapping a processor operation and a bus transaction. Additional performance improvement stems from the balance between several cache factors and careful tuning obtained by means of a simulation phase.