Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors Part 2

Authors:
Milo Tomasevic;Veljko Milutinovic
Affiliations:
-;-
Venue:
IEEE Micro
Year:
1994

Citing 52
Cited 5

Cache coherence protocols: evaluation using a multiprocessor simulation model

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A class of compatible cache consistency protocols and their support by the IEEE futurebus

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Multiprocessor cache synchronization: issues, innovations, evolution

ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
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ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Coherency for multiprocessor virtual address caches

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The cache coherence problem in shared-memory multiprocessors

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Firefly: A Multiprocessor Workstation

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On the inclusion properties for multi-level cache hierarchies

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Multiprocessor cache analysis using ATUM

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A characterization of sharing in parallel programs and its application to coherency protocol evaluation

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The Wisconsin multicube: a new large-scale cache-coherent multiprocessor

ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A cache coherence approach for large multiprocessor systems

ICS '88 Proceedings of the 2nd international conference on Supercomputing
Multilevel cache hierarchies: organizations, protocols, and performance

Journal of Parallel and Distributed Computing
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ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The effect of sharing on the cache and bus performance of parallel programs

ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Evaluating the performance of four snooping cache coherency protocols

ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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Directory-Based Cache Coherence in Large-Scale Multiprocessors

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Cache coherence for large scale shared memory multiprocessors

SPAA '90 Proceedings of the second annual ACM symposium on Parallel algorithms and architectures
Scalable Shared-Memory Multiprocessor Architectures

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Scalable coherent interface

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Stanford distributed-directory protocol

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Aquarius project

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Paradigm: A Highly Scalable Shared-Memory Multicomputer Architecture

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A snooping cache coherency protocol for hierarchically organized multiprocessors

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LimitLESS directories: A scalable cache coherence scheme

ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Comparison of hardware and software cache coherence schemes

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
A performance evaluation of optimal hybrid cache coherency protocols

ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
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Adaptive cache coherency for detecting migratory shared data

ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
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ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Performance analysis of multiprocessor cache consistency protocols using generalized timed Petri nets

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A version control approach to Cache coherence

ICS '89 Proceedings of the 3rd international conference on Supercomputing
Synchronization with multiprocessor caches

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
An empirical evaluation of two memory-efficient directory methods

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Implementing a cache consistency protocol

ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Cache Memories

ACM Computing Surveys (CSUR)
Two economical directory schemes for large-scale cache coherent multiprocessors

ACM SIGARCH Computer Architecture News
RST Cache Memory Design for a Highly Coupled Multiprocessor System

IEEE Micro
Design of an Adaptive Cache Coherence Protocol for Large Scale Multiprocessors

IEEE Transactions on Parallel and Distributed Systems
The Cache Coherence Protocol of the Data Diffusion Machine

PARLE '89 Proceedings of the Parallel Architectures and Languages Europe, Volume I: Parallel Architectures
Using cache memory to reduce processor-memory traffic

ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Dynamic decentralized cache schemes for mimd parallel processors

ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
A low-overhead coherence solution for multiprocessors with private cache memories

ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Simulation Analysis Data Sharing in Shared Memory Multiprocessors

Simulation Analysis Data Sharing in Shared Memory Multiprocessors

A Simulation Study of Hardware-Oriented DSM Approaches

IEEE Parallel & Distributed Technology: Systems & Technology
Distributed Shared Memory: Concepts and Systems

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Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
A Shared-bus Control Mechanism and a Cache Coherence Protocol for a High-performance On-chip Multiprocessor

HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Speeding-up multiprocessors running DBMS workloads through coherence protocols

International Journal of High Performance Computing and Networking

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Abstract

Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors.