Organization and performance of a two-level virtual-real cache hierarchy

  • Authors:

  • W. H. Wang;J.-L. Baer;H. M. Levy

  • Affiliations:

  • Department of Computer Science, FR-35, University of Washington, Seattle, WA;Department of Computer Science, FR-35, University of Washington, Seattle, WA;Department of Computer Science, FR-35, University of Washington, Seattle, WA

  • Venue:
  • ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
  • Year:
  • 1989

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Abstract

We propose and analyze a two-level cache organization that provides high memory bandwidth. The first-level cache is accessed directly by virtual addresses. It is small, fast, and, without the burden of address translation, can easily be optimized to match the processor speed. The virtually-addressed cache is backed up by a large physically-addressed cache; this second-level cache provides a high hit ratio and greatly reduces memory traffic. We show how the second-level cache can be easily extended to solve the synonym problem resulting from the use of a virtually-addressed cache at the first level. Moreover, the second-level cache can be used to shield the virtually-addressed first-level cache from irrelevant cache coherence interference. Finally, simulation results show that this organization has a performance advantage over a hierarchy of physically-addressed caches in a multiprocessor environment.