Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Organization and performance of a two-level virtual-real cache hierarchy
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
A process-dependent partitioning strategy for cache memories
ACM SIGARCH Computer Architecture News
Decomposing memory performance: data structures and phases
Proceedings of the 5th international symposium on Memory management
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