Cache design of a sub-micron CMOS system/370
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
VLSI RISC Architecture and Organization
VLSI RISC Architecture and Organization
Performance '84 Proceedings of the Tenth International Symposium on Computer Performance Modelling, Measurement and Evaluation
Analysis of cache replacement-algorithms
Analysis of cache replacement-algorithms
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This paper presents a method for partitioning cache memories which contain both instruction and data blocks. This partitioning scheme limits the total number of instruction blocks, while no conditions are set on the total number of data blocks. The partitioning is reconfigured by changing the maximum allowed number of instruction blocks, called a “threshold”. A method for choosing this threshold is provided, based on the observation that its optimum value depends on the executable code of the processes considered but almost not on its input data. Trace-driven simulations show that, when medium cache sizes are considered, the proposed structure often yields a much lower miss ratio than the corresponding classical mixed cache (typically 20% to 40% and 50% to 80% lower, respectively if the caches have 4 and 16 ways).