Scalable Shared-Memory Multiprocessor Architectures

Authors:
Shreekant Thakkar;Michael Dubois;Anthony T. Laundrie;Gurindar Sohi
Affiliations:
Sequent Computer Systems, Beaverton, OR;Univ. of Southern California, Los Angeles;Univ. of Wisconsin, Madison;Univ. of Wisconsin, Madison
Venue:
Computer
Year:
1990

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Abstract

Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures.