Multiprocessor cache synchronization: issues, innovations, evolution
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Efficient synchronization primitives for large-scale cache-coherent multiprocessors
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Modeling the performance of limited pointers directories for cache coherence
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors
IEEE Transactions on Computers
Adaptive Proxies: Handling Widely-Shared Data in Shared-Memory Multiprocessors (Research Note)
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Synchronization and cache coherence in computer design
Journal of Computing Sciences in Colleges
Hi-index | 4.10 |
The Stanford distributed-directory (SDD) cache-coherence protocol, based on a singly linked list of distributed directories, is examined. Sharing-list additions and removals are explained diagramatically. Reads, writes, pending signals, replacement, and synchronization are discussed. Replacing lines linked in a list is done by invalidating the lower part of the list. A doubly linked list may be used to patch the list in case of replacements. However, in practice, performance improvement depends on the list lengths and access patterns. A distributed-directory cache-coherence protocol allows efficient implementation of locks at minimal extra cost. The SDD protocol allows a lock implementation that minimizes network traffic