Cache coherence protocols: evaluation using a multiprocessor simulation model
ACM Transactions on Computer Systems (TOCS)
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ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
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The cache coherence problem in shared-memory multiprocessors
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
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ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
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ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
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ACM Computing Surveys (CSUR)
IEEE Transactions on Parallel and Distributed Systems
Boosting the performance of hybrid snooping cache protocols
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
A cost-comparison approach for adaptive distributed shared memory
ICS '96 Proceedings of the 10th international conference on Supercomputing
Analytical Prediction of Performance for Cache Coherence Protocols
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Adaptive software cache management for distributed shared memory architectures
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Minerva: An Adaptive Subblock Coherence Protocol for Improved SMP Performance
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Interactive locality optimization on NUMA architectures
Proceedings of the 2003 ACM symposium on Software visualization
Two Adaptive Hybrid Cache Coherency Protocols
HPCA '96 Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture
Evaluation of cache consistency algorithm performance
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Simulation as a tool for optimizing memory accesses on NUMA machines
Performance Evaluation - Performance modelling and evaluation of high-performance parallel and distributed systems
Cooperative Caching for Chip Multiprocessors
Proceedings of the 33rd annual international symposium on Computer Architecture
vNUMA: a virtual shared-memory multiprocessor
USENIX'09 Proceedings of the 2009 conference on USENIX Annual technical conference
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This paper explores the architecture of high-performance large scale multiprocessors using private caches for each processor. The caches reduce the average memory access time, but they also result in the well known cache coherence problem. Multiple copies of each memory location are allowed to exist but they must be kept consistent with each other. In this paper, we present a solution to the cache coherence problem specifically for shared bus multiprocessors that adapts dynamically to the reference pattern. Simulation results are presented that demonstrate the high level of performance relative to other protocols particularly during intervals with high levels of sharing.The paper then presents a coherence solution for large multiprocessor systems organized around a hierarchy of buses. One of the first solutions of this kind, the hierarchical protocol is an extension of the adaptive shared bus approach described in this paper.