Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System
IEEE Transactions on Computers
Assignment of Tasks in a Distributed Processor System with Limited Memory
IEEE Transactions on Computers
Analysis of Memory Interference in Multiprocessors
IEEE Transactions on Computers
AFIPS '72 (Fall, part II) Proceedings of the December 5-7, 1972, fall joint computer conference, part II
A new minicomputer/multiprocessor for the ARPA network
AFIPS '73 Proceedings of the June 4-8, 1973, national computer conference and exposition
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
IEEE Transactions on Computers
A multiprocessor with replicated shared memory
AFIPS '83 Proceedings of the May 16-19, 1983, national computer conference
| Hi-index | 14.98 |
A multiple-read single-write (MRSW) memory is proposed as a hardware solution to the memory and bus conflict problem in distributed and multiprocessing computing systems. Each memory module is assigned to a host processor which is hardwired to its read-write channel. Its read-only channels are shared by a few closely coupled processors, I/O devices, and/or a data bus which provides access to all other processors. The exact processor-memory organization is determined by a module correlation criteria, which also yields a quantitative measure of the effectiveness of the solution. In a class of scientific computing problems where module correlation is limited to neighboring modules, the memory conflict problem is completely eliminated. The processors may operate as array processors controlled by a CPU, or they may operate autonomously with capabilities of originating programs or transactions. The location conflict problem of multiaccess memories is resolved without additional hardware or delay.