Computer Interconnection Structures: Taxonomy, Characteristics, and Examples
ACM Computing Surveys (CSUR)
On the design of display processors
Communications of the ACM
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Analysis of a Shared Resource MIMD Computer Organization
IEEE Transactions on Computers
Analysis of Multiprocessor Control Organizations with Partial Program Memory Replication
IEEE Transactions on Computers
Parallel Processing with the Perfect Shuffle
IEEE Transactions on Computers
Multiple-Read Single-Write Memory and Its Applications
IEEE Transactions on Computers
Computer
A Survey of Interconnection Networks
Computer
Poolpo A Pool of Processors for Process Control Applications
IEEE Transactions on Computers
Throughput of multiprocessors with replicated shared memories
AFIPS '84 Proceedings of the July 9-12, 1984, national computer conference and exposition
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A multiprocessor includes five 8086 microprocessors interconnected with replicated shared memory. Such a memory structure consists of a set of memories, one for each processor, with identical contents. This minimizes read interference since each processor simply accesses its own private copy of the shared memory. To ensure shared memory integrity, write requests transfer data over the MULTIBUS to all copies in parallel. Overall, replicated shared memory structures provide improved concurrency. An HP 64000 Logic Development System serves as a host computer for program development and a bulk storage device. A power-on and restart monitor in shared PROM provides a run-time debug and method for down-loading the operating system and application programs. The real-time, multi-tasked operating system (called MPX) distributes a sequence of high and low priority tasks, with possible preemption, among the processors. MPX floats from processor to processor while balancing the system load for maximum concurrency and throughput.