Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Implementation of a packet switching device as a delay-insensitive circuit
Proceedings of the 1993 symposium on Research on integrated systems
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Formal Verification of an Arbiter Cascade
Proceedings of the 13th International Conference on Application and Theory of Petri Nets
IEEE Transactions on Computers
IEEE Transactions on Computers
Hi-index | 0.00 |
We present an asynchronous circuit for an arbiter cell that can be used to construct cascaded muitiway arbitration circuits. The circuit is completely speed-independent. It has a short response delay at the input request-grant handshake link due to both a) the propagation of requests in parallel with starting arbitration and b) the concurrent resetting of request-grant handshakes in different cascades of a request-grant propagation chain.