Algebraic structure theory of sequential machines (Prentice-Hall international series in applied mathematics)
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
A functional description of macromodules
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Logical design of macromodules
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
An iteratively structured information processor
ISCA '75 Proceedings of the 2nd annual symposium on Computer architecture
Towards a Theory of Universal Speed-Independent Modules
IEEE Transactions on Computers
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races
IEEE Transactions on Computers
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops
IEEE Transactions on Computers
Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops
IEEE Transactions on Computers
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A transition signal is a change of binary level, either from 0 to 1 or from 1 to 0, regardless of the direction. It is often more convenient to describe a switching circuit in terms of level transitions, and a circuit with at least one input variable represented as a transition signal is called a transition logic circuit. Transition logic circuits are essentially level sequential circuits and, as such, Huffman's synthesis method can be applied. However, Huffman's synthesis rapidly becomes too laborious as the number of transition variables increases. The first part of this paper presents a synthesis approach which is simpler than Huffman's in such cases, although its applicability is more limited. In this approach, one considers a level transition as if it were a pulse, and then synthesizes the circuit following the standard pulse sequential circuit synthesis method. Circuits are constructed from two basic transition logic elements, the G element and the M element, together with ordinary gates.