Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races

  • Authors:
  • J. G. Bredeson;P. T. Hulina

  • Affiliations:
  • -;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1971

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Abstract

A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.