Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
IEEE Transactions on Computers
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Testing delay-insensitive circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
IEEE Transactions on Computers
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
IEEE Design & Test
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
IEEE Transactions on Computers
On Totally Self-Checking Checkers for Separable Codes
IEEE Transactions on Computers
Design of Asynchronous Circuits Assuming Unbounded Gate Delays
IEEE Transactions on Computers
Limitations of VLSI implementation of delay-insensitive codes
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
IEEE Transactions on Computers
Logic-Level Analysis of Fault Attacks and a Cost-Effective Countermeasure Design
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An error-correcting unordered code and hardware support for robust asynchronous global communication
Proceedings of the Conference on Design, Automation and Test in Europe
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