On-Line Testing for VLSI—A Compendium of Approaches
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
Self-Checking Design in Eastern Europe
IEEE Design & Test
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A fault-tolerant permutation network modulo arithmetic processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Methods for designing self-testing checkers (STCs) for arithmetic error-detecting codes are presented. First, general rules for the design of minimal-level STCs for any error-detecting code are given. The design is illustrated with STCs for 3N+B codes, 0or=Bor=2. Then the recursive structure of both 3N+B codes and residue/inverse-residue codes with check base A=3 is revealed. The resulting design of STCs is very flexible and universal, in the sense that an iterative, cost-effective, or high-speed version of the checker can be designed for either code. The design approach, unlike previous approaches for arithmetic codes, gives a unified treatment to STCs for nonseparate (3N+B) and separate (residue and inverse residue) codes. The speed and the complexity of the STC for a code from either class with n bits are about the same. Both high-speed checkers (which have up to three gate levels) and cost-effective checkers are faster and require less hardware than analogous checkers proposed for 3N codes and for residue codes with A=3.