A self-checking generalized prediction checker and its use for built-in testing
IEEE Transactions on Computers
Design of Fast Self-Testing Checkers for a Class of Berger Codes
IEEE Transactions on Computers
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
IEEE Transactions on Computers
Self-Testing Embedded Two-Rail Checkers
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
IEEE Transactions on Computers
IEEE Transactions on Computers
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
IEEE Transactions on Computers
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Low Cost and High Speed Embedded Two-Rail Code Checker
IEEE Transactions on Computers
Comments on "A low-power dependable berger code for fully asymmetric communication"
IEEE Communications Letters
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This paper tackles the open problem of designing combinational self-testing checkers (STCs) for K-pair 2-rail codes which are self-testing, even by a subset of codewords, such that some input lines are 0 (or 1) for only one input codeword. The checker presented here has both theoretical and practical importance. It is useful, e.g., to build STCs for other systematic error detecting codes like Berger codes with I=2k-1 data bits and arithmetic codes with the check base A=2k-1+1, K=3, 4, 5,....It also allows the designers to build functional totally self-checking circuits with 100 percent fault coverage in which such 2-rail codes could not have been used otherwise.